In present packet-switched network architectures, data is transmitted in the form of network packets between computing devices and/or device components at a rapid pace. At a high level, data is packetized into a network packet, which is transmitted by a network interface controller (NIC) of one network computing device and received by a NIC of another network computing device. Upon receipt, the network packet is typically processed, classified, etc., and the payload is typically written to memory (e.g., cache, main memory, etc.). Upon having written the network packet data to memory, the receiving NIC may then notify a host central processing unit (CPU) that the data is available for further processing. However, writing the contents of the network packet data from the NIC to memory for processing by a host CPU can be expensive and introduce latency, or otherwise have some other negative performance impact.